1. Field of the Invention
This invention relates to methods and apparatus for fabrication of fine line and space interconnections in electronic packaging. The invention is in particular applicable for printed circuit boards (PCB), tape automated bonding (TAB) systems and other electronic devices with the need for fine line and space interconnects.
The technical content of PCBs are based on three aspects: density of the electronic circuitry, number of layers, and the quality of material used in lamination of the boards. This invention relates to the first aspect, the density of the board. Density is determined by the relative proximity of the electrically active elements and their number per unit area of the board. The elements that constitute the majority of electrical elements on the board are the copper conductor lines. Hence, the density of the PCB is dependent upon the lateral spacing of the conductor lines and their width.
2. Description of the Prior Art
The trend towards finer lines and decreasing interline spacing has been strong in recent years, and will continue into the future. There have been several particles on this subject. In the article "Shrinking Semiconductors", PC Fabrication, May 1988, R. W. Allison, Jr. and others state that "a steadily decreasing IC line width increases the number of connections to be made on package/board interface. These require an increase in PCB line density and the number of layers in the board." In concurrence with the great majority of authorities in the field they conclude that PCBs with 2 mil-lines will become the standard in the industry in the early 1990s.
In the June 1987 edition of Printed Circuit Fabrication, Vol. 10, No. 6, at pages 37-44, an article by R. D. Rust, entitled "Fine Line Technology: The Impact of Dry Plasma Processing", discusses the supplanting of the wet chemical processes by dry plasma processes for printed circuit fabrication. One of the issues noted by Rust is the need for generation of fine line features of less than four mils. Rust notes that photolithographic resolution is not the limiting process in generating these features; rather, the subsequent processes of developing, etching or plating are the limiting processes.
Conventional printed circuit boards are manufactured in the following manner: the process consists of first joining epoxy and copper laminates by heat and pressure. The epoxy laminate is much thicker than the copper laminate as it provides the mechanical support. Application of heat and pressure causes the epoxy to soften and bond to the copper laminate. The copper surface is either chemically treated, or electrochemically with dendritic treatment, both of which produce a jagged surface on a microscopic scale, which promotes adhesion.
Photo-resist is then applied on the copper surface. Liquid photo-resist application has been replaced lately by `dry` photo-resist methods. In the dry photo-resist technique, a photo-resist film is laminated on the copper again by heat and pressure.
The conductor pattern is then `exposed` on the photo-resist. The exposed board is `developed` in an appropriate chemical solution that dissolves the photo-resist, consequently exposing the copper surface along the area which needed to be etched in the following `copper etching` operation.
In the copper etching operation, the developed board is passed through a chemical spray chamber, where jets spray chemicals which dissolve copper. The photo-resist and the copper etching solution have been so chosen that the chemicals only attack copper and not the photo-resist. At the conclusion of the copper etching process a well defined conductor pattern with an overlay of photo-resist is left on the epoxy substrate.
The photo-resist overlay is then etched away by another chemical solution which only etches the photo-resist and not the copper.
In printed wiring board manufacturing involving `multi-layers`, i.e. boards containing several layers of alternate copper conductors and epoxy laminates, interconnection between the copper conductors on different levels is necessary. That is accomplished by drilling holes at the appropriate levels and depositing copper in the holes, with a prior treatment which assures adhesion of the deposited copper to the epoxy sidewalls.
This etching technology employs an oxidizing solution consisting typically of ferric, cupric or persalfate ions which is sprayed over an imaged laminate. In a subsequent process, copper surfaces protected by an insulating film become part of the circuitry following removal of the film by chemical dissolution.
By the nature of the hydrodynamics of the typical spraying process, the etching solution is unable to penetrate deeper into the recesses formed at levels of less than five mils in spacing. Therefore, the exchange of matter is slowed considerably so that the etching process in narrower spaces is so slow that it does not accomplish the necessary copper removal in comparision with wider spacing. These limitations in mass transport is a major limitation in spray chemical etching process.
Two approaches are known in the art. In one on these methods, the circuitry is made additive. Negative masking leaves openings for the circuitry. Bare substrate in these openings is sensitized with a palladium activator such as employed in electroless copper. Activation is followed by growth of the electroless copper to the required thickness.
Transport of matter is a limiting aspect of this process in the same manner as in the etching process. Other problems with this technique is a low rate of line formation. Problems also occur in the mechanical properties and quality of the formed copper.
Another method employed in the prior art involves electrochemically assisting the chemical etching. In this method, a positive electrical field is applied to the laminate. Electrical contact is typically made at one side of a board. As long as electrical connection is maintained, dissolution occurs both chemically and electrochemically. Problems with this method include resulting electrical discontinuities in the patterns produced.
Derek Pletcher, in his book Industrial Electrochemistry (Chapman & Hall 1982), mentions an electrochemical etching method for making PCBs where the laminated copper with developed photo-resist that exposes only the area to be etched is subjected to a mixture of graphite particles and sulfuric acid. The graphite particles have been previously charged by being in contact with the anode. This process, however, has not proven to be successful on a commercial scale due to the expensive etching method involving the use of graphite, its recovery, and etchants at high concentrations. In addition, this method suffers of standard problems in substrative-technology, i.e. mass transport limitations and the undercutting of the copper with dissolution propagating in all directions with equal rate.